Perpendicularly magnetized magnetic tunnel junctions (p-MTJs) are a major emerging technology for use in embedded MRAM applications, in standalone MRAM applications, and in spin-torque transfer (STT)-MRAM. STT-MRAM is a p-MTJ technology using spin-torque for writing of memory bits that was described by C. Slonezewski in “Current driven excitation of magnetic multilayers”, J. Magn. Magn. Mater. V 159, L1-L7 (1996). P-MTJ technologies that have a high operating speed, low power consumption, excellent endurance, non-volatility, and scalability are highly competitive with existing semiconductor memory technologies such as SRAM, DRAM, and flash.
MRAM and STT-MRAM employ a p-MTJ cell as a switching and storage device. P-MTJs have a general structure wherein an insulating tunnel barrier layer is sandwiched between two magnetic layers. One of the magnetic layers is called the pinned layer and has a magnetization fixed in an out-of-plane direction in the (+z) direction, for example, when the plane of the magnetic layer is formed along the x-axis and y-axis directions. The pinned layer may have a synthetic antiparallel (SyAP) configuration in which an inner magnetic (AP1) layer adjoining the tunnel barrier layer is antiferromagnetically coupled with an outer magnetic (AP2) layer through an intermediate antiferromagnetic coupling (AFC) layer such as Ru. The second magnetic layer called the free layer also has an out-of-plane magnetization with a direction that is free to be either parallel in a (+z) direction (P state) or antiparallel in a (−z) direction (AP state) to that of the AP1 layer. The difference in resistance between the P state (RP) and AP state (RAP) can be characterized by the equation (RAP−RP)/RP that is also known as DRR or the magnetoresistive (MR) ratio. It is important for p-MTJ devices to have a large DRR value since this property is directly related to the read margin for the memory bit, or the ease of differentiating between the P state and AP state (0 or 1 bits).
The stability of the magnetizations for the AP1 and AP2 pinned layers is very important for optimum p-MTJ performance in that the antiparallel alignment of the two layers provides the proper spin current for magnetization switching of the free layer during a write process. Ideally, a single domain is formed in both of the AP1 and AP2 layers. However, as a result of the MRAM fabrication process, multiple domains generally form in both pinned layers. Accordingly, spin current during a write process is often weak and insufficient to switch the free layer magnetization.
In order for p-MTJs to be more competitive with competing memory technologies, write performance must be significantly improved while maintaining the other critical device properties such as DRR. Since STT-MRAM is typically embedded in Complementary Metal Oxide Semiconductor (CMOS) devices, the pinned layer and free layer magnetizations must withstand thermal processing up to 400° C. temperatures.